1. Field of the Invention
The present invention relates to an input buffer which provides an interface between a digital integrated circuit and circuitry external to the digital integrated circuit. More particularly, the present invention relates to an input buffer for a programmable array logic (PAL) device.
2. Description of the Related Art
FIG. 1 shows a block diagram for the AmPALCE22V10, a typical programmable logic device manufactured by Advanced Micro Devices, Inc. The internal circuitry of the AmPALCE22V10 is CMOS logic. To enable the circuitry of the AmPALCE22V10 to be compatible with circuitry external to the chip, which is may be TTL logic, input buffers 100(a-1) are utilized.
The AmPALCE22V10 further includes output logic macrocells 102 connected to provide an output which registered or combinatorial. The output from the output logic macrocell can be fed back into an input buffer on the chip.
FIG. 2 shows typical prior art input buffer, such as that utilized on the AmPALCE22V10. In FIG. 2, an input signal to the input buffer is received by a CMOS inverter 200. In order for the input buffer of FIG. 2 to be TTL compatible, the CMOS inverter 200 should have a threshold at around 1.5 volts, assuming a valid TTL high level is 2.0 volts.
The 1.5 volt threshold is achieved by making the PMOS transistor 202 of inverter 100 relatively weak, or about half the size of the NMOS transistor 204. Note that circles on transistors, such as transistor 202, indicate a P-type transistor, while no circle on a transistor indicates an N-type transistor. With transistor 202 being half the size of transistor 204 inverter 200 has approximately a quarter of the drive capability because of the reduced mobility of holes in relation to electrons.
Note that a TTL high to a standard CMOS input will result in the PMOS 202 not turning off completely so that the first inverter will draw power. Typically, the input would have to be raised to within less than 1.0 volt of the supply voltage for the input stage to not draw power.
To avoid TTL high power consumption, extra steps may be added to a standard CMOS fabrication process to create a PMOS transistor which turns completely off at TTL high input levels.
Inverters 206 and 208 are added to the output of inverter 200 in order to drive a high capacitance node connected to the input buffer output. Note, however, that each inverter added to the signal path of the input buffer has an inherent gate delay so that the decision to add buffering in order to achieve the highest performance is dependent upon the capacitance level of circuitry connected to the output node of the input buffer.